1. Field of the Invention
The present invention relates to an output circuit for a semiconductor memory, and more specifically to an output-data latch circuit for latching a memory read-out signal when a column address strobe signal is inactivated.
2. Description of Related Art
In a so-called page cycle, during a period in which a row address strobe signal RAS is maintained a active, namely, at a low level, a column address strobe signal CAS is alternately activated and inactivated a plurality of times, so that data on memory cells located on a word line selected when the row address strobe signal RAS is brought to the low level are consecutively read out. According to this page cycle, the memory cell data can be read in one cycle of the column address strobe signal CAS, the data on one word can be effectively read out for a short time. Therefore, this page cycle has been widely utilized.
In this page cycle, however, when the column address strobe signal CAS is brought to a high level, an output data is disabled. Therefore, if the cycle period of the column address strobe signal CAS is shortened, an effective period of the 1 output is correspondingly shortened, and accordingly, it has become difficult to control an external device. Under this circumstance, there has been recently developed a semiconductor memory having an extended output function capable of maintaining an output data selected when the column address strobe signal CAS is brought to the low level, even after the column address strobe signal CAS is brought to the high level,
Referring to FIG. 1, there is shown a block diagram illustrating one example of a semiconductor memory having an output circuit.
The semiconductor memory shown in FIG. 1 includes a memory cell array 12 composed of a number of memory cells arranged in the form of a matrix having a plurality of rows and a plurality of columns. The semiconductor memory also includes a plurality of address input terminals 3 for receiving an external address of A.sub.0 to A.sub.n, which is supplied to an address latch circuit 10. The address signal 8 latched in the address latch 10 is supplied to and decoded by an row decoder 11. The row decoder 11 has outputs of the number corresponding to the number of the rows of the memory cell array 12, and each of the outputs of the row decoder 11 is connected to a word line 4 of a corresponding row of the memory cell array 12, so as to select a designated row from the plurality of rows of the memory cell array 12.
The shown semiconductor memory also includes a number of sense amplifiers 13 each connected to a corresponding column or the plurality of columns of the memory cell array 12, and a column decoder 14 connected to receive the output 8 of the address latch 10 and having a plurality of outputs 5 connected to corresponding columns of the memory cell array 12, respectively, so as to select a designated column from the plurality of columns of the memory cell array 12. An output of the sense amplifier 13 connected to the column selected by the column decoder 14 is supplied to a read amplifier 14, which in turn has an output 6 connected to an output circuit 16. An output of the output circuit 16 is connected to an output terminal 7.
A row address strobe signal RAS on an input terminal 1 is supplied to the address latch 10 and the sense amplifier 13, and the column address strobe signal CAS on an input terminal 2 is also supplied to the address latch 10 and the output circuit 16.
Since the above mentioned construction of the semiconductor memory is fundamental and well known to persons skilled in the art, further detailed explanation of the construction and description of operation will be omitted.
Referring to FIG. 2, there is shown a logic circuit diagram of a conventional output circuit having an extended function, which is incorporated as the output circuit 16 in the semiconductor memory shown in FIG. 1. The shown output circuit is configured to receive the output 6 of the read amplifier 16 and the column address strobe signal CAS and to output an output data to the output terminal 7.
The shown output circuit includes an inverter 24 receiving the column address strobe signal CAS, and another inverter 25 receiving the output 6 of the read amplifier 16. An output of the inverter 24 constitutes an output data latch signal 9, which is supplied to one input of each of two NAND gates 20 and 22. The output 6 of the read amplifier 16 is supplied to the other input of the NAND gate 20, and an output of the inverter 25 is supplied to the other input of the NAND gate 22 as a data signal complimentary to the data signal supplied to the NAND gate 20. An output of the NAND gate 20 is connected to one input of a NAND gate 21, and an output of the NAND gate 22 is connected to one input of a NAND gate 23. An output of the NAND gate 21 is connected to the other input of the NAND gate 23, and an output of the NAND gate 23 is connected to the other input of the NAND gate 21. Thus, a flipflop is formed by a pair of NAND gates 2l and 23, and a data latch circuit is constituted of the four NAND gates 20, 21, 22 and 23.
The output of the NAND gates 21 and 23 are connected to a gate of a pair of field effect transistors 26 and 27, connected in series between a positive power supply voltage and the ground. A connection node between the series-connected field effect transistors 26 and 27 is connected to the output terminal 7:
Referring to FIG. 3, there is shown a timing chart of the row address strobe signal RAS, the column address strobe signal CAS, external address (A.sub.0 to A.sub.n), the column decoder output signal 5, the read amplifier output signal 6, the output data latch signal 9.
Operation of the semiconductor memory will be described with reference to FIGS. 1, 2 and 3.
If the row address strobe signal RAS is brought to the low level at the time t.sub.1, the external address (A.sub.0 to A.sub.n) is latched in the address latch 10 as a row address A.sub.x, and therefore, the row decoder 11 selects or activates one word line of the plurality of word lines 4. Thereafter, the sense amplifier 13 is activated, so that information of memory cells on the selected word line is amplified. At the time t.sub.2, if the column address strobe signal CAS is brought to the low level, the external address (A.sub.0 to A.sub.n) is latched in the address latch 10 as a column address A.sub.C1, and therefore, the column decoder 14 outputs an output A.sub.DC1 so as to select a designated bit line, so that the information of the designated memory cell is outputted through the read amplifier 15 to the output circuit 16 as data D.sub.1.
At this time, since the column address strobe signal CAS is at the low level, the data latch signal 9 is at the high level. Therefore, the data latch circuit constituted of the four NAND gates 20, 21, 22 and 23 is put in a pass-through condition, so that the output D.sub.1 of the read amplifier 15 is outputted from the output terminal 7 as an output data D.sub.01.
Thereafter, if the column address strobe signal CAS is brought to the high level, an external address A.sub.C2 to be used in a next read cycle is supplied, and the column decoder 15 selects the bit line corresponding the newly supplied external address AC.sub.2. Accordingly, a new memory cell data is supplied through the read amplifier 15 to the output circuit 16.
In this process, the output circuit 16 continues to output the memory cell information selected when the column address strobe signal CAS is brought to the low level, during a period in which the column address strobe signal CAS is maintained at the high level, namely, during an extended outputting period. Accordingly , the previous output data D.sub.O1 is maintained even after the column address strobe signal CAS is brought to the high level until the time t.sub.4 where the column address strobe signal CAS is brought to the low level for a next cycle.
After the time t.sub.4, the memory cell information selected by the column address AC.sub.2 is amplified the read amplifier 15 and outputted through the output circuit 16 to the output terminal as the output data D.sub.O2.
As will be apparent from the above, the above mentioned function-extended output circuit of the semiconductor memory is configured so that just after the rising of the column address strobe signal CAS, the memory cell data is latched in the output circuit. Accordingly, in the case that the column address is setup time is short with reference to the falling of the column address strobe signal CAS, if the column address strobe signal CAS is brought of the high level during a period after an address is supplied and a memory cell is selected until information of the selected memory cell is supplied through the read amplifier to the output circuit, the selected memory cell information cannot be outputted. Because of this, the column address strobe signal CAS has to be maintained at the low level which is longer than the ordinary case. In other words, the low level period of the column address strobe signal CAS is restricted by the column address setup time, and therefore, cannot be shortened.
This means that the cycle of the column address strobe signal CAS itself for reading the memory cell data can be made shorter than that of a semiconductor memory having no extended output function